The present invention relates to an electronic data processing system, and more particularly to a method and apparatus for arbitrating for control of a high speed direct memory access (DMA) bus within the system.
Modern microprocessors are typically rich in data processing capabilities. They often have hundreds of instructions that instruct their respective systems to READ, WRITE, and process (logically and/or arithmetically) information. The instructions and the information are typically READ, WRITTEN and processed using data words ranging from one to 16 bytes in length. Because of this data word orientation, it is not surprising that microprocessors lack the capabilities to rapidly move large blocks of data words, such as would be necessary for file transfers from a SCSI input/output device which could involve 10 kilobytes or more of information.
In recognition of this inability to perform high speed block transfers, many microprocessor based systems are supplemented with DMA controllers to increase their overall data transfer rate. The DMA controller can transfer large blocks of data between memory (e,g, random access memory or RAM) and any device which uses blocks data (e,g. SCSI peripheral devices).
The DMA controller typically connects to the system memory via the processor address and data buses in the same manner that the microprocessor is connected to these buses. In such a configuration, the microprocessor and the DMA controller time share the control and use of these buses. But, having the DMA controller share control of the processor address and data buses with the microprocessor has led to some difficult problems. Many of these problems occur because control of the processor address and data buses is passed from the microprocessor to the DMA controller at the beginning of each DMA storage/retrieval transaction. The overhead time required to periodically transfer control of these buses from the microprocessor to the DMA controller is fairly large. So large, in fact, that it is a bottleneck to high speed peripheral sub-systems, such as a SCSI controller and a SCSI bus. To provide lower overhead times and prevent this bottleneck, some systems have added dedicated high speed DMA buses which connect to their system memories. But even in a system with a dedicated high speed DMA bus, the microprocessor is typically blocked from accessing either the dedicated DMA bus or the DMA sub-system devices associated with the dedicated DMA bus until the present DMA transaction is completed. This can be especially troublesome if the DMA controller is unable to successfully complete the present DMA transaction, as occasionally happens. In such a case, the DMA controller may wait for the transaction to be completed, but that completion never occurs. The system DMA controller is not sophisticated enough to time itself out (i.e. set a maximum time limit for a transaction and then terminate the transaction if the limit is exceeded), and the system microprocessor, which is sophisticated enough to time itself or the DMA controller out, is blocked from a normal access until the normal access is completed. Thus, there is a need in the art for a system having a microprocessor and a DMA controller wherein the microprocessor can rapidly access the DMA sub-system devices at virtually any time.
It is an object of this invention to provide a data processing system with a microprocessor, a DMA controller, and a high speed DMA memory bus, wherein the high speed DMA memory bus may be used by the microprocessor to check the status of any DMA device between DMA cycles of a DMA data transaction.
It is another object of this invention to provide a DMA controller for use in a system with a high speed DMA data bus which has an arbitration circuit such that the system microprocessor may arbitrate for access to the high speed address and data buses even during a current DMA cycle of a DMA transaction.